View HN58S256AT-20_1250884.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HN58S256A Series
256 k EEPROM (32-kword x 8-bit)
ADE-203-692B (Z) Rev. 2.0 Nov. 1997 Description
The Hitachi HN58S256A is a electrically erasable and programmable EEPROM's organized as 32768word x 8-bit employing advanced MNOS memory technology and CMOS process and circuitry technology. It also has a 64-byte page programming function to make the write operations faster.
Features
* Single supply: 2.2 to 3.6 V * Access time: 150 ns (max)/200 ns (max) * Power dissipation: Active: 10 mW/MHz, (typ) Standby: 36 W (max) * On-chip latches: address, data, CE, OE, WE * Automatic byte write: 15 ms (max) * Automatic page write (64 bytes): 15 ms (max) * Data polling and Toggle bit * Data protection circuit on power on/off * Conforms to JEDEC byte-wide standard * Reliable CMOS with MNOS cell technology * 105 erase/write cycles (in page mode) * 10 years data retention * Software data protection * Industrial versions (Temperatur range:-40 to 85C) are also available.
HN58S256A Series
Ordering Information
Type No. HN58S256AT-15 HN58S256AT-20 Access time 150 ns 200 ns Package 28-pin plastic TSOP (TFP-28DB)
Pin Arrangement
HN58S256AT Series A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 (Top view) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A4 A5 A6 A7 A12 A14 VCC WE A13 A8 A9 A11 OE
Pin Description
Pin name A0 to A14 I/O0 to I/O7 OE CE WE VCC VSS Function Address input Data input/output Output enable Chip enable Write enable Power supply Ground
HN58S256A Series
Block Diagram
I/O0 High voltage generator
to
VCC VSS
I/O7
OE CE WE Control logic and timing
I/O buffer and input latch
A0
to
Y decoder
Y gating
A5 Address buffer and latch A6
to
X decoder
Memory array
A14
Data latch
Operation Table
Operation Read Standby Write Deselect Write inhibit CE VIL VIH VIL VIL x x Data polling VIL OE VIL x*
2
WE VIH x VIL VIH VIH x VIH
I/O Dout High-Z Din High-Z -- -- Data out (I/O7)
VIH VIH x VIL VIL
Notes: 1. Refer to the recommended DC operating condition. 2. x = Don't care
HN58S256A Series
Absolute Maximum Ratings
Parameter Power supply voltage relative to V SS Input voltage relative to V SS Operationg temperature range* Storage temperature range
2
Symbol VCC Vin Topr Tstg
Value -0.6 to +4.6 -0.5* to +4.6* 0 to +70 -55 to +125
1 3
Unit V V C C
Notes: 1. Vin min = -3.0 V for pulse width 50 ns 2. Including electrical characteristics and data retention 3. Should not exceed VCC + 1.0 V.
Recommended DC Operating Conditions
Parameter Supply voltage Symbol VCC VSS Input voltage VIL VIH Operating temperature Topr Notes: 1. VIL min: -1.0 V for pulse width 50 ns. 2. VIH max: VCC + 1.0 V for pulse width 50 ns. Min 2.2 0 -0.3*
1
Typ 3.0 0 -- -- --
Max 3.6 0 0.4
2
Unit V V V C
Vcc x 0.7 0
VCC + 0.3* V 70
DC Characteristics (Ta = 0 to +70 C, VCC = 2.2 to 3.6 V)
Parameter Input leakage current Output leakage current Standby V CC current Symbol I LI I LO I CC1 I CC2 Operating VCC current I CC3 Min -- -- -- -- -- -- Output low voltage Output high voltage VOL VOH -- VCC x 0.8 Typ -- -- -- -- -- -- -- -- Max 2 2 10 500 8 12 0.4 -- Unit A A A A mA mA V V Test conditions VCC = 3.6 V, Vin = 0 to 3.6 V VCC = 3.6 V, Vout = 3.6/0.4 V, CE = VIH, Vin = 0 to 3.6 V CE = VCC CE = VIH Iout = 0 mA, Duty = 100%, Cycle = 1 s at VCC = 3.6 V Iout = 0 mA, Duty = 100%, Cycle = 150 ns at VCC = 3.6 V I OL = 1.0 mA I OH = -100 A
HN58S256A Series
Capacitance (Ta = 25C, f = 1 MHz)
Parameter Input capacitance*
1 1
Symbol Cin Cout
Min -- --
Typ -- --
Max 6 12
Unit pF pF
Test conditions Vin = 0 V Vout = 0 V
Output capacitance* Note:
1. This parameter is periodically sampled and not 100% tested.
AC Characteristics (Ta = 0 to +70 C, VCC = 2.2 to 3.6 V)
Test Conditions * * * * * Input pulse levels: 0.4 V to 1.9 V (V CC 2.7V), 0.4V to 2.4 V (VCC > 2.7 V) Input rise and fall time: 5 ns Input timing reference levels: 0.8, 1.8 V Output load: 1TTL Gate +100 pF Output reference levels: 1.1 V, 1.1 V (V CC 2.7V),1.5 V, 1.5 V (V CC > 2.7 V)
Read Cycle
HN58S256A -15 Parameter Address to output delay CE to output delay OE to output delay Address to output hold OE (CE) high to output float*
1
-20 Max 150 150 80 -- 100 Min -- -- 10 0 0 Max 200 200 100 -- 100 Unit ns ns ns ns ns Test conditions CE = OE = VIL, WE = VIH OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = VIL, WE = VIH
Symbol t ACC t CE t OE t OH t DF
Min -- -- 10 0 0
HN58S256A Series
Write Cycle
Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled) WE to write setup time (CE controlled) WE hold time (CE controlled) OE to write setup time OE hold time Data setup time Data hold time WE pulse width (WE controlled) CE pulse width (CE controlled) Data latch time Byte load cycle Byte load window Write cycle time Write start time Symbol t AS t AH t CS t CH t WS t WH t OES t OEH t DS t DH t WP t CW t DL t BLC t BL t WC t DW Min*2 0 150 0 0 0 0 0 0 150 0 200 200 200 0.4 100 -- 0*
4
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- -- -- -- -- -- -- -- 30 -- 15* --
3
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s ms ns
Test conditions
Notes: 1. t DF is defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. Use this device in longer cycle than this value. 3. t WC must be longer than this value unless polling techniques is used. This device automatically completes the internal write operation within this value. 4. Next read or write operation can be initiated after t DW if polling techniques is used. 5. A6 through A14 are page addresses and these addresses are latched at the first falling edge of WE. 6. A6 through A14 are page addresses and these addresses are latched at the first falling edge of CE. 7. See AC characteristics.
HN58S256A Series
Timing Waveforms
Read Timing Waveform
Address tACC CE tCE OE tOE WE High tDF tOH
Data Out
Data out valid
Byte Write Timing Waveform (1) (WE Controlled)
tWC Address tCS CE tAS WE tOES OE tDS Din tDH tOEH tBL tAH tCH
tWP
HN58S256A Series
Byte Write Timing Waveform (2) (CE Controlled)
Address tWS CE tAS WE tOES tOEH OE tDS Din tDH tAH tCW tBL tWC
tWH
Page Write Timing Waveform (1) (WE Controlled)
*5
Address A0 to A14
tAS WE tCS CE tOES OE
tAH tWP tDL tCH tBLC
tBL
tWC
tOEH tDH
tDS
Din
HN58S256A Series
Page Write Timing Waveform (2) (CE Controlled)
*5
Address A0 to A14 CE
tAS
tAH tCW tDL tBLC
tBL
tWS WE tOES OE tDS
tWH
tWC
tOEH tDH
Din
Data Polling Timing Waveform
Address
An
An
An
CE
WE
tOEH
tCE *7
tOES
OE tOE*7 I/O7 Din X Dout X Dout X tWC tDW
HN58S256A Series
Toggle bit This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming cycle, I/O6 will charge from "1" to "0" (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program. Toggle bit Waveform Notes: 1. 2. 3. 4. I/O6 beginning state is "1". I/O6 ending state will vary. See AS read characteristics. Any address location can be used, but the address must be fixed.
Next mode
*4
Address tCE *3 CE
WE tOE OE tOEH
*1 *2 *2
*3
tOES
I/O6
Din
Dout
Dout tWC
Dout
Dout tDW
HN58S256A Series
Software Data Protection Timing Waveform (1) (in protection mode)
VCC
CE
WE tBLC Address Data 5555 AA 2AAA 55 5555 A0 Write address Write data tWC
Software Data Protection Timing Waveform (2) (in non-protection mode)
VCC
tWC
Normal active mode
CE
WE
Address Data
5555 2AAA 5555 5555 2AAA 5555 AA 55 80 AA 55 20
HN58S256A Series
Functional Description
Automatic Page Write Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 s from the preceding falling edge of WE or CE. When CE or WE is high for 100 s after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Data Polling Data polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM is performing a write operation. WE, CE Pin Operation During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of WE or CE. Write/Erase Endurance and Data Retention Time The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed less than 104 cycles.
HN58S256A Series
Data Protection 1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. To prevent this phenomenon, this device has a noise cancelation function that cuts noise if its width is 20 ns or less in program mode. Be careful not to allow noise of a width of more than 20 ns on the control pins.
WE CE
VIH 0V
OE
VIH 0V
20 ns max
HN58S256A Series
2. Data Protection at VCC On/Off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state. Note: The EEPROM shoud be kept in unprogrammable state during VCC on/off by using CPU RESET signal.
VCC CPU RESET * Unprogrammable
* Unprogrammable
(1) Protection by CE, OE, WE To realize the unprogrammable state, the input level of control pins must be held as shown in the table below.
CE OE WE VCC x x x VSS x x x VCC
x: Don't care. VCC: Pull-up to VCC level. VSS : Pull-down to V SS level.
HN58S256A Series
3. Software data protetion To prevent unintentional programming caused by noise generated by external circuits. This device has the software data protection function. In software data protection mode, 3 bytes of data must be input before write data as follows. And these bytes can switch the non-protection mode to the protection mode. SDP is not enabled if only the 3 bytes code is input.
Address Data
5555 AA 2AAA 55 5555 A0 Write address Write data } Normal data input
Software data protection mode can be cancelled by inputting the following 6 bytes. After that, this device turns to the non-protection mode and can write data normally. But when the data is input in the cancelling cycle, the data cannot be written.
Address 5555 2AAA 5555 5555 2AAA 5555 Data AA 55 80 AA 55 20
The software data protection is not enabled at the shipment. Note: There are some differences between Hitachi's and other company's for enable/disable sequence of software data protection. If there are any questions , please contact with Hitachi sales offices.
HN58S256A Series
Package Dimensions
HN58S256AT Series (TFP-28DB)
Unit: mm 8.00 8.20 Max 28 15
1
14 0.55
0.22 0.08 0.10 M 0.20 0.06 0.45 Max
11.80
13.40 0.30 0 - 5 0.17 0.05 0.15 0.04
0.80
1.20 Max
0.10
0.13 -0.08
+0.07
0.50 0.10
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC Code EIAJ Code Weight (reference value)
TFP-28DB -- -- 0.23 g
HN58S256A Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071

▲Up To Search▲

Price & Availability of HN58S256AT-20

	To Download HN58S256AT-20 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .